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FDD8874 / FDU8874
o
April 2008
FDD8874 / FDU8874
N-Channel PowerTrench(R) MOSFET 30V, 116A, 5.1m
General Description
This N-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low rDS(ON) and fast switching speed.
tm
Features
* rDS(ON) = 5.1m VGS = 10V, ID = 35A , , * rDS(ON) = 6.4m VGS = 4.5V, ID = 35A * High performance trench technology for extremely low rDS(ON) * Low gate charge
Applications
* DC/DC converters
* High power and current handling capability
*
RoHS Compliant
D G S
I-PAK (TO-251AA) GDS
G
D
D-PAK TO-252 (TO-252)
S
MOSFET Maximum Ratings TC = 25C unless otherwise noted
Symbol VDSS VGS Parameter Drain to Source Voltage Gate to Source Voltage Drain Current Continuous (TC = 25oC, VGS = 10V) (Note 1) ID Continuous (TC = Pulsed EAS PD TJ, TSTG Single Pulse Avalanche Energy (Note 2) Power dissipation Derate above 25oC Operating and Storage Temperature 25oC, VGS = 4.5V) (Note 1) Continuous (Tamb = 25oC, VGS = 10V, with RJA = 52oC/W) 116 103 18 Figure 4 240 110 0.73 -55 to 175 A A A A mJ W W/oC
oC
Ratings 30 20
Units V V
Thermal Characteristics
RJC RJA RJA Thermal Resistance Junction to Case TO-252, TO-251 Thermal Resistance Junction to Ambient TO-252, TO-251 Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area 1.36 100 52
o o
C/W C/W
oC/W
(c)2008 Fairchild Semiconductor Corporation
FDD8874 / FDU8874 Rev. B2
FDD8874 / FDU8874
Package Marking and Ordering Information
Device Marking FDD8874 FDU8874 F F Device FDD8874 FDU8874 Package TO-252AA TO-251AA Reel Size 13" Tube Tape Width 12mm N/A (Tube) Quantity 2500 units 75 units
Electrical Characteristics TC = 25C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BVDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250A, VGS = 0V VDS = 24V VGS = 0V VGS = 20V TC = 150oC 30 1 250 100 V A nA
On Characteristics
VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250A ID = 35A, VGS = 10V rDS(ON) Drain to Source On Resistance ID = 35A, VGS = 4.5V ID = 35A, VGS = 10V, TJ = 175oC 1.2 2.5 V 0.0042 0.0051 0.0052 0.0064 0.0069 0.0083
Dynamic Characteristics
CISS COSS CRSS RG Qg(TOT) Qg(5) Qg(TH) Qgs Qgs2 Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance Total Gate Charge at 10V Total Gate Charge at 5V Threshold Gate Charge Gate to Source Gate Charge Gate Charge Threshold to Plateau Gate to Drain "Miller" Charge (VGS = 10V) VDD = 15V, ID = 35A VGS = 10V, RGS = 4.7 9 96 47 37 156 126 ns ns ns ns ns ns VDS = 15V, VGS = 0V, f = 1MHz VGS = 0.5V, f = 1MHz VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 15V ID = 35A Ig = 1.0mA 2990 585 340 2.0 54 29 3.0 8.0 5.0 10 72 38 4.0 pF pF pF nC nC nC nC nC nC
Switching Characteristics
tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time
Drain-Source Diode Characteristics
VSD trr QRR Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ISD = 35A ISD = 15A ISD = 35A, dISD/dt = 100A/s ISD = 35A, dISD/dt = 100A/s 1.25 1.0 32 18 V V ns nC
Notes: 1: Package current limitation is 35A. 2: Starting TJ = 25C, L = 0.61mH, IAS = 28A, VDD = 27V, VGS = 10V. 3
(c)2008 Fairchild Semiconductor Corporation
FDD8874 / FDU8874 Rev.B2
FDD8874 / FDU8874
Typical Characteristics TC = 25C unless otherwise noted
1.2 120 CURRENT LIMITED BY PACKAGE ID, DRAIN CURRENT (A) 90
POWER DISSIPATION MULTIPLIER
1.0
0.8
0.6
60
0.4
30 VGS = 10V 0 25 50 75 100 125 150 175 TC, CASE TEMPERATURE (oC)
0.2
0 0 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs Case Temperature
2 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01
Figure 2. Maximum Continuous Drain Current vs Case Temperature
ZJC, NORMALIZED THERMAL IMPEDANCE
PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-3 10-2 t, RECTANGULAR PULSE DURATION (s) 10-1 100 101
SINGLE PULSE 0.01 10-5 10-4
Figure 3. Normalized Maximum Transient Thermal Impedance
1000 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION IDM, PEAK CURRENT (A) VGS = 4.5V I = I25 VGS = 10V 100
TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 175 - TC 150
30 10-5 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101
Figure 4. Peak Current Capability
(c)2008 Fairchild Semiconductor Corporation
FDD8874 / FDU8874 Rev.B2
FDD8874 / FDU8874
Typical Characteristics TC = 25C unless otherwise noted
1000 10s ID, DRAIN CURRENT (A) 100 100s 10 IAS, AVALANCHE CURRENT (A) 100 500 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON)
STARTING TJ = 25oC 10
1ms 10ms DC
1 SINGLE PULSE TJ = MAX RATED TC = 25oC 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 60
STARTING TJ = 150oC
1 0.1
1 10 tAV, TIME IN AVALANCHE (ms)
100
Figure 5. Forward Bias Safe Operating Area
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching Capability
100
100 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V ID, DRAIN CURRENT (A)
VGS = 10V 80 VGS = 5V 60
VGS = 4V
80 ID , DRAIN CURRENT (A)
60 TJ = 40 25oC
VGS = 3V
40
TC = 25oC PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
20 TJ = 175oC 0 1.5 TJ = -55oC
20 VGS = 2.5V 0 2.0 2.5 3.0 VGS , GATE TO SOURCE VOLTAGE (V) 3.5 0 0.2 0.4 0.6 0.8 VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics
14 NORMALIZED DRAIN TO SOURCE ON RESISTANCE ID = 35A rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) 12 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
Figure 8. Saturation Characteristics
1.8 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 1.6
1.4
10
1.2
8
1.0
6 ID = 1A 4 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V)
0.8 VGS = 10V, ID = 35A 0.6 -80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)
Figure 9. Drain to Source On Resistance vs Gate Voltage and Drain Current
Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature
(c)2008 Fairchild Semiconductor Corporation
FDD8874 / FDU8874 Rev.B2
FDD8874 / FDU8874
Typical Characteristics TC = 25C unless otherwise noted
1.2 VGS = VDS, ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.10 ID = 250A
NORMALIZED GATE THRESHOLD VOLTAGE
1.0
1.05
0.8
1.00
0.6
0.95
0.4 -80
-40
0
40
80
120
160
200
0.90 -80
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
TJ , JUNCTION TEMPERATURE (oC)
Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature
5000
Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature
10 VDD = 15V VGS , GATE TO SOURCE VOLTAGE (V)
CISS = CGS + CGD C, CAPACITANCE (pF) CRSS = CGD COSS CDS + CGD
8
1000
6
4 WAVEFORMS IN DESCENDING ORDER: ID = 35A ID = 1A 0 10 20 30 40 Qg, GATE CHARGE (nC) 50 60
2
VGS = 0V, f = 1MHz 100 0.1 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 30
0
Figure 13. Capacitance vs Drain to Source Voltage
Figure 14. Gate Charge Waveforms for Constant Gate Current
(c)2008 Fairchild Semiconductor Corporation
FDD8874 / FDU8874 Rev.B2
FDD8874 / FDU8874
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP 0V RG IAS VDD VDD tP VDS
+
IAS 0.01 0 tAV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
VDS VDD L VGS VDS Qg(5) VDD DUT Ig(REF) VGS = 1V 0 Qg(TH) Qgs Ig(REF) 0 Qgd Qgs2 VGS = 5V Qg(TOT) VGS VGS = 10V
+
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON td(ON) RL VDS 90% tr
tOFF td(OFF) tf 90%
VGS
+
VDD DUT 0
10%
10%
RGS VGS VGS 0 10% 50% PULSE WIDTH
90% 50%
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
(c)2008 Fairchild Semiconductor Corporation
FDD8874 / FDU8874 Rev.B2
FDD8874 / FDU8874
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
( T JM - TA ) P DM = ----------------------------R JA
125 RJA = 33.32+ 23.84/(0.268+Area) EQ.2 100 RJA (oC/W) RJA = 33.32+ 154/(1.73+Area) EQ.3
75
(EQ. 1)
50
In using surface mount devices such as the TO-252 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 21 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads.
25 0.01 (0.0645)
0.1 (0.645)
1 (6.45)
10 (64.5)
AREA, TOP COPPER AREA in2 (cm2)
Figure 21. Thermal Resistance vs Mounting Pad Area
R JA = 33.32 + -----------------------------------154 ( 1.73 + Area )
23.84 ( 0.268 + Area )
(EQ. 2)
Area in Inches Squared
R JA = 33.32 + ---------------------------------
(EQ. 3)
Area in Centimeters Squared
(c)2008 Fairchild Semiconductor Corporation
FDD8874 / FDU8874 Rev.B2
FDD8874 / FDU8874
PSPICE Electrical Model
.SUBCKT FDD8874 2 1 3 ; rev May 2004 Ca 12 8 2.1e-9 Cb 15 14 2.1e-9 Cin 6 8 2.7e-9
10 LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + 17 EBREAK 18 MWEAK MMED MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 RBREAK 18 RVTEMP 19 7 SOURCE 3 DRAIN 2 RSLC1 51 ESLC 50 RDRAIN EVTHRES + 19 8 6 21 16
RSLC2
ESG + LGATE GATE 1 RLGATE EVTEMP RGATE + 18 22 9 20 6 8
It 8 17 1 Lgate 1 9 6.5e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 1.8e-9 RLgate 1 9 65 RLdrain 2 5 10 RLsource 3 7 18 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 2e-3 Rgate 9 20 2.0 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 2e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),10))} .MODEL DbodyMOD D (IS=7E-12 IKF=10 N=1.01 RS=2.5e-3 TRS1=8e-4 TRS2=2e-7 + CJO=1.2e-9 M=0.57 TT=1e-15 XTI=1.2) .MODEL DbreakMOD D (RS=8e-2 TRS1=1e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=9.2e-10 IS=1e-30 N=10 M=0.37) .MODEL MmedMOD NMOS (VTO=1.8 KP=9 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.0) .MODEL MstroMOD NMOS (VTO=2.2 KP=380 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=1.49 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=20 RS=0.1) .MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-8e-7) .MODEL RdrainMOD RES (TC1=6.7e-3 TC2=7e-6) .MODEL RSLCMOD RES (TC1=1e-4 TC2=1e-6) .MODEL RsourceMOD RES (TC1=1e-4 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-2.1e-3 TC2=-8e-6) .MODEL RvtempMOD RES (TC1=-1.8e-3 TC2=2e-7) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-0.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-2) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
(c)2008 Fairchild Semiconductor Corporation
-
Ebreak 11 7 17 18 33.5 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1
5 51
+
Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD
DBODY
FDD8874 / FDU8874 Rev.B2
FDD8874 / FDU8874
SABER Electrical Model
rev May 2004 template FDD8874 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=7e-12,ikf=10,nl=1.01,rs=2.5e-3,trs1=8e-4,trs2=2e-7,cjo=1.2e-9,m=0.57,tt=1e-15,xti=1.2) dp..model dbreakmod = (rs=8e-2,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=9.2e-10,isl=10e-30,nl=10,m=0.37) m..model mmedmod = (type=_n,vto=1.8,kp=9,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=2.2,kp=380,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=1.49,kp=0.05,is=1e-30, tox=1,rs=0.1) LDRAIN sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3) DPLCAP 5 sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3,voff=-4) 10 sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2,voff=-0.5) RLDRAIN RSLC1 sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=-2) 51 c.ca n12 n8 = 2.1e-9 RSLC2 c.cb n15 n14 = 2.1e-9 ISCL c.cin n6 n8 = 2.7e-9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 33.5 GATE spe.eds n14 n8 n5 n8 = 1 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1 l.lgate n1 n9 = 6.5e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 1.8e-9
CA 12 S1B 13 + EGS 6 8 EDS LGATE ESG + EVTEMP RGATE + 18 22 9 20 6 MSTRO CIN 8 6 8 EVTHRES + 19 8 50 RDRAIN 21 16 MWEAK MMED EBREAK + 17 18 DBREAK 11 DBODY
DRAIN 2
RLGATE
LSOURCE 7 RLSOURCE
SOURCE 3
RSOURCE S1A 13 8 S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 RBREAK 18 RVTEMP 19
res.rlgate n1 n9 = 65 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 18 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=8.3e-4,tc2=-8e-7 res.rdrain n50 n16 = 2e-3, tc1=6.7e-3,tc2=7e-6 res.rgate n9 n20 = 2.0 res.rslc1 n5 n51 = 1e-6, tc1=1e-4,tc2=1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 2e-3, tc1=1e-4,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-2.1e-3,tc2=-8e-6 res.rvtemp n18 n19 = 1, tc1=-1.8e-3,tc2=2e-7 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 10)) } }
(c)2008 Fairchild Semiconductor Corporation
FDD8874 / FDU8874 Rev.B2
FDD8874 / FDU8874
PSPICE Thermal Model
REV 23 May 2004 FDD8874T CTHERM1 TH 6 1.9e-3 CTHERM2 6 5 2.8e-3 CTHERM3 5 4 3.5e-3 CTHERM4 4 3 3.6e-3 CTHERM5 3 2 4.0e-3 CTHERM6 2 TL 1.6e-2 RTHERM1 TH 6 3.8e-2 RTHERM2 6 5 5.0e-2 RTHERM3 5 4 1.0e-1 RTHERM4 4 3 1.8e-1 RTHERM5 3 2 3.5e-1 RTHERM6 2 TL 3.7e-1
th
JUNCTION
RTHERM1
CTHERM1
6
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model FDD8874T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =1.9e-3 ctherm.ctherm2 6 5 =2.8e-3 ctherm.ctherm3 5 4 =3.5e-3 ctherm.ctherm4 4 3 =3.6e-3 ctherm.ctherm5 3 2 =4.0e-3 ctherm.ctherm6 2 tl =1.6e-2 rtherm.rtherm1 th 6 =3.8e-2 rtherm.rtherm2 6 5 =5.0e-2 rtherm.rtherm3 5 4 =1.0e-1 rtherm.rtherm4 4 3 =1.8e-1 rtherm.rtherm5 3 2 =3.5e-1 rtherm.rtherm6 2 tl =3.7e-1 }
RTHERM3 CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
(c)2008 Fairchild Semiconductor Corporation
FDD8874 / FDU8874 Rev.B2
TRADEMARKS
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(R)
tm
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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. This datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only.
Rev. I34
Preliminary
First Production
No Identification Needed Obsolete
Full Production Not In Production
@2008 Fairchild Semiconductor Corporation
FDD8874 / FDU8874 Rev. B2

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